Memory cells are circuits wherein information may be stored in a low current stand-by mode and may be written or read in a higher current mode. A predetermined number of cells are located in a row between each of a plurality of upper and lower word lines and another predetermined number of cells are located in a column between a plurality of bit lines. In other words, each cell is uniquely coupled between a combination of word lines and bit lines.
A row of cells is selected when increased voltage is supplied to the upper word line. A particular cell in that row is read by a sense amplifier coupled to the bit lines. A first read current through one bit line flows directly from the sense amplifier. A second read current through the other bit line flows through one side of the memory cell from the upper word line. When a cell is written, the first read current is directed through the cell and the second read current is directed from the sense amplifier.
There are generally two types of previously known write circuits: single ended and differential. The single ended write circuit pulls down the base of a first sense amplifier device while the base of a second sense amplifier device remains at a read threshold with a read current flowing in the memory cell until it is almost fully written. The differential write circuit raises the base of the second sense amplifier device to remove the read current from the memory cell.
Previously known differential write circuits included current sources coupled between the memory cell and ground by the bit lines. A first and a second decode transistor have their collector-emitter path coupled between the bit lines and the current sources, respectively, and are biased by a column decode circuit for steering write currents through the bit lines. A sense amplifier is coupled to the bit lines above the memory cell for sensing which side of the cell has been written. The read current for the "on" side of the memory cell goes to zero. The sense amplifier typically comprises a first and second transistor, each having an emitter connected to one of the bit lines for supplying current thereto, a base connected to a write circuit for biasing one of the first or second transistors during the write mode, and a collector connected to a first and a second node, respectively. A third and fourth transistor have their bases connected to a bias voltage, their emitters connected to the first and second nodes, respectively, and their collectors coupled to a first supply voltage terminal by a first and second resistor, respectively. The first and second nodes are coupled to a second supply voltage terminal by a first and second current source, respectively. The collectors of the third and fourth transistors are further connected to an output gate for providing an output signal.
However, the voltage on one side of the sense amplifier must be taken towards the upper supply voltage to remove the read current from the "on" side of the memory cell, but there generally is not enough voltage differential to allow this due to the presence of the third and fourth transistors.
Therefore, a current steering differential write circuit is needed that forces one side of the sense amplifier down while diverting current from the other bit line to improve cell response to the write signal.